1. Technical Field
The present invention relates to an input and output driver and, more specifically, to an input and output driver capable of effectively reducing an input capacitance (Cin) of a double data rate (DDR)-III product.
2. Discussion of Related Art
Double data rate (DDR)-III standard graphic DRAM products require a channel impedance of 40Ω in which at least 30Ω tuning is supported. Furthermore, an on-die termination (ODT) circuit, which is provided to match impedance between a graphic processor unit (GPU) and a graphic DRAM (GDRAM), requires impedance of about 60Ω. Furthermore, in the GDRAM, the input capacitance Cin is limited to 3 pF or less to insure transmission of signal wave forms at the time of high-speed operation of 700 MHz level.
Generally, a DQ pin for transmitting and receiving data is connected to complex circuit elements, such as an input buffer, an output driver, an electrostatic discharge protection circuit (herein after, referred to as “ESD”), and an ODT circuit. Thus, the input capacitance Cin including a capacitance component due to a package is easily over 3 pF. Accordingly, improvement in the field of elements or processes is required.
Furthermore, increase in the capacitance due to an ODT switch transistor necessary for the ODT circuit makes it very difficult to satisfy requirements for the input capacitance Cin. An increase in the memory operation frequency requires a decrease in the maximum allowable value of the input capacitance. Therefore, in order to reduce the input capacitance Cin, synthetic improvements, such as improvements in design approach and decreases in relevant processes and design rules, are required.